In a nonvolatile semiconductor memory device such as a NAND flash memory, data is written for each page. In the NAND flash memory, however, it is difficult to correctly write data in all cells by a write operation at one time. The write operation of the NAND flash memory is divided into three processes: (1) write, (2) verify read (verify), and (3) search/count of cells that have not ended the write (fail bits).
Processes 1 to 3 are repeated until the number of fail bits has equaled or fallen below the number of allowable bits (the allowable the number of fail bits) in process 3, or the write count has reached the maximum. The fail bit search/count in process 3 is called a scan. A NAND flash memory chip normally has a plurality of kinds of scan operations corresponding to write characteristics such as accuracy and speed.
There is proposed, for example, a method (bit scan) of detecting an error for each bit, counting the number of fail bits, and determining whether the number of fail bits is less than or equal to the number of allowable bits. In this bit scan, an entire page is scanned at a time, and it is determined for each page whether the number of fail bits is less than or equal to the number of allowable bits.
Recently, the number of fail bits increases as the micropatterning and multilevel cell technologies advance, or the page length increases. This leads to a requirement to increase the number of allowable bits. In the above-described bit scan, however, since the scan operation is performed for an entire page, the increase in the number of allowable bits has a limit.